The present invention relates to a timing analyzing method and apparatus for a semiconductor integrated circuit.
When a semiconductor integrated circuit is designed, timing analysis is performed taking into consideration gate delay, which is caused by cells forming the semiconductor integrated circuit, and net delay, which is caused by wiring (conductive paths) connecting the cells. The layout of the semiconductor integrated circuit is corrected based on the timing analysis results. The gate delay changes in accordance with the power supply voltage and the ambient temperature. The net delay changes in accordance with the ambient temperature. Thus, the timing analysis and layout correction must be performed taking into consideration the parameters of the power supply voltage and the ambient temperature.
The operation delay time of a semiconductor integrated circuit changes in accordance with the power supply voltage, the ambient temperature, and process conditions. Process conditions result from changes in the delay time caused by differences in a semiconductor manufacturing process. A process having a long delay time is referred to as a slow process, and a process having a short delay time is referred to as a fast process.
Among the various combinations of the power supply voltage, the ambient voltage, and the process conditions, there are two extreme conditions, which are referred to as the worst-case corner condition and the best-case corner condition. The worst-case corner condition is normally the harshest condition from the viewpoint of timing error occurrences caused by changes in the operation delay time. The worst-case corner condition is referred to as a first corner condition and is the combination of high temperature (upper limit temperature), low voltage (lower limit voltage), and slow process. The best-case corner condition is referred to as a second corner condition and is the combination of low temperature (lower limit temperature), high voltage (upper limit voltage), and fast process.
However, the ratio of the gate delay and the wire delay (net delay) may differ between a clock path (transfer path of clock signal) and a data path (transfer path of data signal). In this case, the temperature characteristics of the gate delay differ from the temperature characteristics of the net delay. Thus, the two corner conditions may not be critical conditions.
The following table shows an example of the changing rate in the net delay and the gate delay resulting from temperature changes.
TABLE 1Increasing Rate Under Low Temperature,High Voltage ConditionsNet DelayGate DelayLow Temperature,1.01.0High VoltageHigh Temperature,about 1.62 (1.625)about 1.27 (1.254)High Voltage
For example, when the net delay and gate delay of a signal path under a low temperature and high voltage is 1.0, the net delay under a high temperature and high voltage is about 1.62 times greater and the gate delay is 1.27 times greater. In other words, the increasing rte of the delay time caused by a temperature rise is greater in the net delay.
Therefore, in each signal path of a semiconductor integrated circuit, the two corner conditions described above may not be critical conditions due to the difference in occupying rate of the net delay and the gate delay.
FIG. 1 shows an example of a data path and a clock path in a semiconductor integrated circuit. In FIG. 1, data path dp transmits a data signal to a flip-flop circuit 2b via a plurality of buffer circuits 1 and a flip-flop circuit 2a. A clock path cp transmits a clock signal to a flip-flop circuit 2b via a plurality of buffer circuits 3.
Under the second corner condition (low temperature, high voltage, and fast process), a margin analysis was conducted on the delay time of the data path dp, the delay time of the clock path cp, and the hold time of the flip-flop circuit 2b. The results are shown by the following equations.Data path delay=Net delay (221.5 ps)+Gate delay (1353.8 ps)=1575.3 psNet delay ratio=221.5 ps/1575.3 ps=0.14Clock path delay=Net delay (689.3 ps)+Gate delay (782.6 ps)=1471.9 psNet delay ratio=689.3 ps/1471.9 ps=0.47Hold Margin=Data path delay−Clock path delay−Hold=1575.3 ps−1471.9 ps−62.0 ps=41.4 ps  (equation 1)
In the analysis results, the data path delay is the total delay time of the data path dp, or the sum of the net delay and gate delay in the data path dp, and is 1575.3 ps. The net delay ratio is the ratio of the net delay relative to the total delay time. The net delay ratio of the data path dp is 0.14.
The clock path delay is the total delay time of the clock path cp, or the sum of the net delay and gate delay in the clock path cp, and is 1471.9 ps. The net delay ratio of the clock path cp is 0.47.
The hold margin is the margin relative to the hold time Hold required by the flip-flop circuit 2b and is 41.4 ps.
Accordingly, under the first corner condition, a hold margin having a positive value is ensured. Thus, timing errors do not occur.
Timing analysis was conducted under the second corner condition (high temperature, high voltage, and fast process) in which the temperature was changed to a high temperature. The results are shown by the following equations.Data path delay=Net delay (358.7 ps)+Gate delay (1729.0 ps)=2087.7 ps (1.33 times longer)Clock path delay=Net delay (1116.1 ps)+Gate delay (986.7 ps)=2102.8 ps (1.43 times longer)Hold Margin=Data path delay−Clock path delay−Hold=2087.7 ps−2102.8 ps−82.0 ps=−97.1 ps  (equation 2)
In this analysis result, the net delay and gate delay are obtained by multiplying the net delay and gate delay under the first corner condition by the increasing rate shown in table 1. The hold margin of −97.1 is obtained from the data path delay and the clock path delay. This indicates a timing error.
As described above, even if the timing analysis is performed under the first and second corner conditions, the detection of a timing error cannot be ensured. Therefore, a multi-corner timing analysis is performed. In addition to the first and second corner conditions, the multi-corner timing analysis uses a third corner condition, which is a combination of high temperature, high voltage, and fast process, and a fourth corner condition, which is a combination of low temperature, low voltage, and slow process.
FIG. 2 shows a multi-corner timing analysis method of the prior art. Four libraries 4a to 4d store delay information including the net delay and gate delay of each cell under the first to fourth corner conditions.
A delay calculation, crosstalk (X-talk) analysis, and timing analysis are performed under each of the corner conditions. Based on the analysis result and slack information, a layout correction process, or timing engineering change (EC) process, is performed. The slack information indicates a set up time margin when increasing the data bus delay time to ensure the hold time of the flip-flop circuit.
FIGS. 3A and 3B show specific examples of the above timing analysis and layout correction process. In the circuit of FIG. 3A, for example, under the second corner condition (low temperature, high voltage, and fast process), the net delay of the data path dp is 16 ps, the gate delay of the data path dp is 70 ps, the slack time of the flip-flop circuit 5 is 5 ps, the standard hold timing value is 30 ps, the net delay of the clock path cp is 30 ps, and the gate delay of the clock path cp is 20 ps. In this case, the hold margin of the flip-flop circuit 5 is obtained from the following equation.Hold Margin=86 ps (70+16)−50 ps (20+30)−30 ps=6 ps  (equation 3)
In this case, a hold margin of 6 ps is obtained. Thus, a timing error does not occur.
In the circuit of FIG. 3A, for example, under the third corner condition (high temperature, high voltage, and fast process), which is obtained by changing the temperature to a high temperature in the second corner condition (low temperature, high voltage, and fast process), the net delay of the data path dp is 25.6 ps, the gate delay of the data path dp is 77 ps, the slack time of the flip-flop circuit 5 is 11 ps, the standard hold timing value is 35 ps, the net delay of the clock path cp is 48 ps, and the gate delay of the clock path cp is 22 ps. The hold margin of the flip-flop circuit 5 is obtained from the following equation.Hold Margin=102.6 ps−70 ps−35 ps=−2.4 ps  (equation 4)
In this case, the hold margin is insufficient by −2.4. This indicates a timing error.
To solve the timing error under the third condition, as shown in FIG. 3B, a buffer circuit 6 is added to the data path dp to increase the delay time of the data path dp. More specifically, the slack time of the flip-flop circuit has a margin of 11 ps. Thus, the buffer circuit 6 having a gate delay of 11 ps is added to the data path dp.
The addition of the buffer circuit 6 increases the gate delay of the data path dp from 77 ps to 88 ps. The slack time becomes zero, and a hold margin of 8.6 ps is obtained for the flip-flop circuit 5 as shown by the following equation. Thus, a timing error does not occur.Hold Margin=113.6 ps−70 ps−35 ps=8.6 ps  (equation 5)
However, the addition of the buffer circuit 6 increases the gate delay from 70 ps to 81 ps also under the second corner condition. Thus, the slack time becomes insufficient, and a timing error occurs.
In this manner, when a layout correction is performed to obtain a hold margin that does not cause a timing error under any one of the corner conditions, a timing error may occur under other corner conditions.